With a development of high density and high integration of a semiconductor integrated circuit (LSI) used for electronics device, higher pin count and finer pitch of connecting terminals of LSI chip have been rapidly developed in recent years. The LSI chip is mounted over a circuit substrate by generally employing a flip-chip mounting process in order to decrease wiring delay. It is common practice in this flip-chip mounting process to form solder bumps on the connecting terminals of the LSI chip, and then connect, through such solder bumps, all the connecting terminals to all electrodes formed on the circuit substrate in a batch process.
For mounting a next-generation LSI having 5000 or more connecting terminals over the circuit substrate, it is required to form fine-pitch bumps with its pitch of 100 μm or less. It is, however, difficult for a conventional solder bump forming process to form such fine-pitch bumps. Moreover, from a viewpoint that a large number of bumps must be formed according to the number of the connecting terminals, a high productivity is required for reducing a manufacturing cost by reducing mounting tact time per chip.
Conventionally, there has been developed a plating process and a screen printing process as a bump forming process. The plating process is convenient for achieving the fine pitch, but it is complicated and has to compromise the productivity. The screen printing process, on the other hand, has a high productivity, but is not convenient for achieving the fine pitch since a mask is used.
Recently, there has been developed several processes for selectively forming solder bumps on electrodes of the LSI chip or circuit substrate. These processes are not only convenient for forming fine bumps, but also convenient for achieving a high productivity since a plurality of the fine bumps can be formed in a batch process. Accordingly they are expected as promising processes that can be applicable to the mounting of the next-generation LSI over the circuit substrate.
According to one of these promising processes, there is a solder paste process (for example, see Japanese Patent Kokai Publication No. 2000-94179 which is hereinafter referred to also as “Patent literature 1”). In this process, a solder paste comprising a mixture of metal particles and a flux is applied directly onto a substrate having electrodes thereon, and subsequently the substrate is heated so as to melt the metal particles. As a result, the bumps are formed selectively on the electrodes having high wettability.
There is also another process called as a super solder paste process wherein a paste composition (“deposition type solder using chemical reaction”) mainly comprising organic acid lead salt and tin metal is applied directly onto a substrate having electrodes thereon, and subsequently the substrate is heated so as to induce a displacement reaction for Pb and Sn, and thereby Pb/Sn alloy is selectively deposited on electrodes of the substrate. For example, see Japanese Patent Kokai Publication No. H01-157796 (which is hereinafter referred to also as “Patent literature 2”).
Both of the solder paste process and the super solder paste processes involve local variations in thickness and concentration of the solder, because the paste composition is applied onto the substrate. This causes the deposition amount of the solder to differ from one electrode to another, and therefore their processes cannot form bumps which are all equal in height. As to such processes, the paste composition is applied onto the substrate of which surface is not smooth due to the electrodes formed thereon. As a result, less amount of the solder is supplied on the electrodes having a higher level than that of the substrate surface, and thus it is difficult to form the bumps with satisfactory heights required for the flip-chip mounting.
By the way, in a flip-chip mounting process employing a conventional bump forming technique, subsequent to mounting a semiconductor chip over a circuit substrate having bumps formed thereon, it is required that a resin (which is called “underfill”) is poured into a clearance gap formed between the circuit substrate and the semiconductor chip so as to secure the semiconductor chip to the circuit substrate.
There has been developed a flip-chip mounting process using an anisotropic conductive material wherein opposing electrode terminals of a semiconductor chip and a circuit substrate are electrically connected to each other, and at the same time the semiconductor chip is secured to the circuit substrate. For example, see Japanese Patent Kokai Publication No. 2000-332055 (which is hereinafter referred to also as “Patent literature 3”). In this process, a thermosetting resin comprising electrically conductive particles is supplied between the circuit substrate and the semiconductor chip, and subsequently the semiconductor chip is pressed and at the same time the thermosetting resin is heated. As a result, the electrical connection between the electrode terminals of the semiconductor chip and the circuit substrate, and the securing of the semiconductor chip to the circuit substrate are concurrently achieved.    Patent literature 1: Japanese Patent Kokai Publication No. 2000-94179    Patent literature 2: Japanese Patent Kokai Publication No. H01-157796    Patent literature 3: Japanese Patent Kokai Publication No. 2000-332055    Patent literature 4: Japanese Patent Kokai Publication No. 2004-260131    Non-patent literature 1: 10th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 5-6, 2004, pp. 183-188    Non-patent literature 2: 9th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 6-7, 2003, pp. 115-120